Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures

3D Tree Cache – A Novel Approach to Non- Uniform Access Latency Cache Architectures for 3D CMPs

We consider a non-uniform access latency cache architecture (NUCA) design for 3D chip multiprocessors (CMPs) where cache structures are divided into small banks interconnected by a network-on-chip (NoC). In earlier NUCA designs, data is placed in banks either statically (S-NUCA) or dynamically (D-NUCA). In both SNUCA and D-NUCA designs, scaling to hundreds of cores can pose several challenges. ...

3D Tree Cache – A Novel Approach to Non- Uniform Access Latency Cache Architectures for 3D CMPs

This paper studies a new query on uncertain data, called k-selection query. Given an uncertain dataset of N objects, where each object is associated with a ranking score and a presence probability, a k-selection query returns k objects such that the expected ranking score of the best available objects is maximized. This query is useful in several applications such as information retrieval and d...

Many Core Hardware Architectures

Many-Task Computing on Many-Core Architectures

Many-Task Computing (MTC) is a common scenario for multiple parallel systems, such as cluster, grids, cloud and supercomputers, but it is not so popular in shared memory parallel processors. In this sense and given the spectacular growth in performance and in number of cores integrated in many-core architectures, the study of MTC on such architectures is becoming more and more relevant. In this...

Energy efficient cache architectures for single, multi and many core processors

With each technology generation we get more transistors per chip. Whilst processor frequencies have increased over the past few decades, memory speeds have not kept pace. Therefore, more and more transistors are devoted to on-chip caches to reduce latency to data and help achieve high performance. On-chip caches consume a significant fraction of the processor energy budget but need to deliver h...